This invention relates to memory management technology for controlling access to and monitoring availability of memory resources. More particularly, this invention relates to memory management technology for managing memory access requests to a common memory shared by multiple requesting entities.
A typical computer system includes one or more common memory systems. Illustrated at 200 of FIG. 1 is a portion of such a computer system. This portion of a computer system illustrates memory resources that are shared by multiple devices and sub-systems.
In particular, the focus here is on primary memory rather than secondary memory. Examples of such primary memory include RAM, ROM, DRAM, SRAM, and other such physical memories. Herein, primary memory may be generally called xe2x80x9cRAMxe2x80x9d, xe2x80x9cmain memoryxe2x80x9d, or xe2x80x9csystem memory.xe2x80x9d
Such primary memory includes physical memory, which, for example, refers to the actual chips capable of holding data. Primary memory does not include virtual memory, which expands physical memory onto secondary memory. Examples of secondary memory includes hard drives, floppy disks, CD-ROM, or any other memory where memory access is significantly slower than that of primary memory.
Common Memory
Primary memory is often shared amongst multiple devices and sub-systems. This shared memory may be called a xe2x80x9ccommon memory,xe2x80x9d such as common memory subsystem 201. The devices and sub-systems that may access the memory are generally called xe2x80x9cagentsxe2x80x9d or xe2x80x9centities.xe2x80x9d Examples of agents are shown in FIG. 1, they include processor(s) 202, communications (Input Output or I O) device(s) 204, disk controller(s) 203, other hardware devices 205 (such as memory scrubbers), and the like. Each of these agents may send an access request to the common memory subsystem 201 in system 200 when an agent wishes to read from or write to memory.
FIG. 2 shows a general schematic view of components of common memory subsystem 201. In particular, the subsystem 201 includes an I/O unit 220, other memory hardware 224, and a memory 230. As the name suggests, the I/O unit 220 handles the subsystem""s communications with agents. The memory 230 is the core of the subsystem. This is the actual memory. The other memory hardware 224 handles any other tasks that need to be performed, such as facilitating output of data from the memory 230 and facilitating access requests to the memory. These access requests typically involve a combination of tasks. Such tasks include one or more reads from and one or more writes to the memory.
To provide order to otherwise unregulated access to the common memory 230, the other memory hardware 224 may employ a memory management strategy. The most common strategy is to simply place all requests into a FIFO (first-in, first-out) queue. Therefore, in the order in which requests are received, each request gets to use the memory to perform its tasks.
Latency
Latency is the measure of time between the moment when a memory request is made until the moment that the result of such request is returned to the requesting agent. If an agent has its own memory that is unshared, one would expect the latency for a specified task to be the same each time that task is performed. However, when there is a memory shared amongst many agent, then the latency of such a task varies depending upon how long the task must wait to have access to the common memory.
Agents time-share the common memory subsystem 201. This means that each agent gets a slice of time to perform its tasks (as it has requested). If one assumes that there are agents waiting to use the memory, some of these uses are more urgent than other uses. Therefore, it is desirable to minimize such latencyxe2x80x94particularly for such urgent uses.
There are other reasons a request to access memory may be delayed. There is additional waiting when the operational speeds of the memory subsystem 201, the agents 202-205, and the links between the subsystem and agents are not in-sync. For example, a processor may operate at 500 MHz, its link (called a bus) to the memory subsystem may operate at 100 MHz, and the memory subsystem may operate at 300 MHz. In this example, the components and links are operating at different speeds; therefore, there may be gaps between tasks performed by an access request.
Furthermore, additional delay is occurs because the memory""s access protocol, which controls access to the memory. This protocol consumes several clock cycles to initiate and perform each read from memory. Likewise, it consumes several clock cycles to initiate and perform each write to memory. These clock cycles are merely overhead where no working data is read from or written to memory.
Described herein is an improved memory management technology for controlling access to and monitoring availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests.
This summary itself is not intended to limit the scope of this patent. For a better understanding of the present invention, please see the following detailed description and appending claims, taken in conjunction with the accompanying drawings. The scope of the present invention is pointed out in the appending claims.